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| 1990 16/8 bit single-chip microcomputer data sheet mos integrated circuit m pd78p368a 1996 the m pd78p368a is produced by replacing the internal mask rom of the m pd78366a with a one-time prom or eprom. one-time prom products, in which data can be written once are effective for manufacture of small quantities of multiple products and early stage start-up of application. eprom products, to which programs can be re-written after previously written programs have been erased, are suited for system evaluation. the following user's manual describes the details of functions. be sure to read it before design. m pd78366a user's manual, hardware: u10205e m pd78356 user's manual, instructions: ieu-1395 features ? compatible with the m pd78366a ? can be replaced with the m pd78366a containing mask rom on a full-production basis. ? internal prom: 48k bytes ? data can be written once (one-time prom product without an erasure window) ? written data can be erased by exposure to ultraviolet light and re-written electrically (eprom product with an erasure window) ? prom programming characteristics: compatible with the m pd27c1001a ? qtop tm microcomputer remark the qtop microcomputer is a single-chip microcomputer with a built-in one-time prom that is totally supported by nec. the support includes writing application programs, marking, screening, and verification. ordering information part number package internal rom m pd78p368agf-3b9 80-pin plastic qfp (14 20 mm) one-time prom m pd78p368akl-s note 80-pin ceramic wqfn eprom note under development in this manual, the description of the prom is for both a one-time prom and eprom. the information in this document is subject to change without notice. the mark h shows major revised points. document no. u11373ej1v0ds00 (1st edition) (previous no. ip-3680) date published june 1996 p printed in japan
2 m pd78p368a pin configuration (top view) (1) normal operation mode (mode0 = l, mode1 = l) ? 80-pin plastic qfp (14 20 mm) m pd78p368agf-3b9 ? 80-pin ceramic wqfn m pd78p368akl-s caution directly connect the ic pin to v ss. remark pin compatible with the m pd78366agf p52/a10 p51/a9 p50/a8 p47/ad7 p46/ad6 p45/ad5 p44/ad4 p43/ad3 p42/ad2 p41/ad1 p40/ad0 v ss v dd av dd av ref p77/ani7 p76/ani6 p75/ani5 p74/ani4 p73/ani3 p72/ani2 p71/ani1 p70/ani0 av ss v ss p00/rtp0 p01/rtp1 p02/rtp2 p03/rtp3 p04/pwm0 p05/ tcud/pwm1 p06/ tiud/to40 p07/ tclrud wdto ic v dd v ss x1 x2 mode1 p30/ t x d0 p33/si/sbi p34/sck p35/ t x d1 p36/r x d1 p10 p11 p12 p13 p14 p16 p17 mode0 p20/nmi p21/intp0 p22/intp1 p23/intp2 p24/intp3/ ti p25/intp4 p85/ to05 p84/ to04 p83/ to03 p81/ to01 p80/ to00 astb p93 p92 p91/ wr p90/rd p57/a15 p56/a14 p55/a13 p54/a12 p53/a11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 v ss p32/so/sb0 p82/ to02 p31/r x d0 reset p15 3 m pd78p368a p00-p07: port 0 p10-p17: port 1 p20-p25: port 2 p30-p36: port 3 p40-p47: port 4 p50-p57: port 5 p70-p77: port 7 p80-p85: port 8 p90-p93: port 9 rtp0-rtp3: real-time port nmi: nonmaskable interrupt intp0-intp4: interrupt from peripherals to00-to05, to40: timer output ti: timer input tiud: timer input for up/down counter tcud: timer control for up/down counter tclrud: timer clear for up/down counter ani0-ani7: analog input txd0, txd1: transmit data rxd0, rxd1: receive data si: serial input so: serial output sb0, sb1: serial bus sck: serial clock pwm0, pwm1: pulse width modulation output wdto: watchdog timer output mode0, mode1: mode ad0-ad7: address/data bus a8-a15: address bus astb: address strobe rd: read strobe wr: write strobe reset: reset x1, x2: crystal av dd : analog v dd av ss : analog v ss av ref : analog reference voltage v dd : power supply v ss : ground ic: internally connected 4 m pd78p368a (2) prom programming mode (mode0/v pp = h, mode1 = l) ? 80-pin plastic qfp (14 20 mm) m pd78p368agf-3b9 ? 80-pin ceramic wqfn m pd78p368akl-s caution symbols in parentheses denote how the pins not used in the prom programming mode should be treated. l: connect these pins to the v ss pins through separate resistors. g: connect these pins to the v ss pins. open: do not connect these pins to anything. d7 d6 d5 d4 d3 d2 d1 d0 v ss v dd v dd v ss a0 a1 a2 a3 a4 a5 a6 a7 (open) (g) v dd v ss (g) (open) mode1 (g) a16 mode0/ v pp a9 a8 a15 a14 a13 a11 a10 pgm ce oe 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 v ss a12 (l) (l) (l) (g) (l) (g) (l) 5 m pd78p368a a0-a16: address bus d0-d7: data bus ce: chip enable oe: output enable pgm: programming mode mode0, mode1: programming mode set v pp : programming power supply v dd : power supply v ss : ground 6 m pd78p368a block diagram note shading indicates the pins used in the prom programming mode. programmable interrupt controller timer/counter unit (real-time pulse unit) serial interface real-time output port nmi intp sck txd rxd rtp exu main ram general registers data memory alu micro sequence control micro rom a/d converter watchdog timer port bcu system control & bus control & prefetch control prom/ram periph- eral ram p0 p1 p2 p3 p7 p8 p9 v dd v ss 2 4 wdto av dd av ss av ref ani prom 48k 8 & to ti tiud tcud so/sb0 si/sb1 pwm pwm p5 p4 8 8 6 7 8 8 8 6 4 2 4 7 5 8 (sbi) (uart) 128 8 & 128 8 1792 8 x1 x2 reset astb rd wr d0-d7 pgm mode0/ v pp note a8-a15 mode1 ce oe a0-a16 ad0-ad7 note 8 8 17 8 tclrud 2 2 5 4 intp2 7 m pd78p368a contents 1. pin functions ........................................................................................................................ 8 1.1 normal operation mode (mode0 = l, mode1 = l) ......................................................... 8 1.2 prom programming mode (mode0/v pp = h, mode1 = l) ................................................ 10 1.3 input/output circuit type for each pin and handling of unused pins .......... 11 2. memory configuration ................................................................................................... 13 3. differences between the m pd78p368a and m pd78366a ......................................... 14 4. prom programming ............................................................................................................ 15 4.1 operation mode ........................................................................................................................ 15 4.2 procedure for writing on prom (page program mode) ............................... 16 4.3 procedure for writing on prom (byte program mode) ................................ 18 4.4 procedure for reading from prom ........................................................................... 21 5. erasure characteristics ( m pd78p368akl-s only) ................................................ 22 6. protective film covering the erasure window ( m pd78p368akl-s only) ........ 22 7. screening one-time prom products .......................................................................... 22 8. electrical specifications ............................................................................................. 23 9. package drawings ............................................................................................................. 39 10. recommended soldering conditions ...................................................................... 41 appendix a tools ...................................................................................................................... 42 a.1 development tools ................................................................................................................ 42 a.2 embedded software ............................................................................................................... 47 appendix b dimensions of the conversion socket and recommended pattern on boards ......................................................................................... 49 h h 8 m pd78p368a 1. pin functions 1.1 normal operation mode (mode0 = l, mode1 = l) (1) port pins function i/o dual-function pin pin name p00-p03 p04 p05 p06 p07 p10-p17 p20 p21 p22 p23 p24 p25 p30 p31 p32 p33 p34 p35 p36 p40-p47 p50-p57 p70-p77 i/o i/o i i/o i/o i/o i port 0. 8-bit i/o port. can be specified as input or output bit by bit. port 1. 8-bit i/o port. can be specified as input or output bit by bit. port 2. port used only for 6-bit input. port 3. 7-bit i/o port. can be specified as input or output bit by bit. port 4. 8-bit i/o port. can be specified as input or output in units of 8 bits. port 5. 8-bit i/o port. can be specified as input or output bit by bit. port 7. port used only for 8-bit input. p80-p85 p90 p91 p92 p93 i/o i/o port 8. 6-bit i/o port. can be specified as input or output bit by bit. port 9. 4-bit i/o port. can be specified as input or output bit by bit. to00 - to05 rd wr C C rtp0-rtp3 pwm0 tcud/pwm1 tiud/to40 tclrud C nmi intp0 intp1 intp2 intp3/ti intp4 txd0 rxd0 so/sb0 si/sb1 sck txd1 rxd1 ad0-ad7 a8-a15 ani0-ani7 9 m pd78p368a (2) non-port pins (1/2) function dual-function pin pin name rtp0-rtp3 nmi intp0 intp1 intp2 intp3 intp4 ti tcud tiud tclrud to00-to05 to40 ani0-ani7 txd0 txd1 rxd0 rxd1 sck si so sb0 sb1 pwm0 pwm1 wdto ad0-ad7 a8-a15 astb rd wr p00-p03 p20 p21 p22 p23 p24/ti p25 p24/intp3 p05/pwm1 p06/to40 p07 p80-p85 p06/tiud p70-p77 p30 p35 p31 p36 p34 p33/sb1 p32/sb0 p32/so p33/si p04 p05/tcud C p40-p47 p50-p57 C p90 p91 i/o outputs a pulse in real time as triggered by a trigger signal sent from the real-time pulse unit. nonmaskable interrupt request input external interrupt request input external count clock input to timer 1 input for the control signal to determine whether the up/down counter (timer 4) counts up or down. external count clock input to the up/down counter (timer 4) clear signal input to the up/down counter (timer 4) pulse output from the real-time pulse unit analog input to the a/d converter serial data output from the asynchronous serial interface serial data input to the asynchronous serial interface serial clock i/o for the clock synchronous serial interface serial data input to the clock synchronous serial interface in the 3-wire mode serial data output from the clock synchronous serial interface in the 3-wire mode serial data i/o for the clock synchronous serial interface in the sbi mode pwm signal output output for the signal which indicates the watchdog timer overflowed. (a nonmaskable interrupt is generated.) multiplexed address/data bus used when external memory is expanded address bus used when external memory is expanded output for the timing signal used in externally latching address information output from the ad0 to ad7 and a8 to a15 pins, in order to access the external memory read strobe signal output to the external memory write strobe signal output to the external memory o i i o i o i i/o i o i/o o o i/o o 10 m pd78p368a (2) non-port pins (2/2) 1.2 prom programming mode (mode0/v pp = h, mode1 = l) function i/o dual-function pin pin name mode0 mode1 reset x1 x2 av ref av dd av ss v dd v ss ic input for the control signal which sets the operation mode. normally, both mode0 and mode1 are directly connected to the v ss pin. system reset input crystal input pin for the system clock. a clock signal provided externally is input to the x1 pin. the reversed signal of the clock signal is input to the x2 pin. a/d converter reference voltage input analog power supply for the a/d converter ground for the a/d converter positive power supply ground internally connected. directly connect the ic pin to v ss . C C C C C C C C C i i i C i C C C C C i/o i i i i/o i i i function prom programming mode set/programming supply voltage prom programming mode set address bus data bus program input enable prom read strobe to prom positive power supply gnd pin name mode0/v pp mode1 a0-a16 d0-d7 pgm ce oe v dd v ss 11 m pd78p368a 1.3 input/output circuit type for each pin and handling of unused pins table 1-1 lists the input and output circuit type for each pin and how to handle it when it is not used. fig. 1-1 shows the circuits. table 1-1 input/output circuit type for each pin and recommended connection methods for unused pins recommended connection method i/o circuit type pin 5-a 2 2-a 5-a 8-a 5-a 9 5-a 5 19 1 2 C p00/rtp0-p03/rtp3 p04/pwm0 p05/tcud/pwm1 p06/tiud/to40 p07/tclrud p10-p17 p20/nmi p21/intp0 p22/intp1 p23/intp2 p24/intp3/ti p25/intp4 p30/txd0 p31/rxd0 p32/so/sb0 p33/si/sb1 p34/sck p35/txd1 p36/rxd1 p40/ad0-p47/ad7 p50/a8-p57/a15 p70/ani0-p77/ani7 p80/to00-p85/to05 p90/rd p91/wr p92, p93 astb wdto mode0, mode1 reset av ref , av ss av dd input state: each pin is connected to the v dd or v ss pin via a separate resistor. output state: open connected to the v ss pin. input state: each pin is connected to the v dd or v ss pin via a separate resistor. output state: open connected to the v ss pin. input state: each pin is connected to the v dd or v ss pin via a separate resistor. output state: open connected to the v ss pin. C connected to the v ss pin. connected to the v dd pin. 12 m pd78p368a fig. 1-1 input/output circuits of each pin type 1 type 5-a type 2 type 8-a type 2-a type 9 type 5 type 19 in v dd p-ch n-ch schmitt trigger input with hysteresis characteristics in pull-up enable p-ch in schmitt trigger input with hysterisis characteristics v dd data output disable v dd in/out input enable p-ch n-ch input enable output disable pull-up enable data in/out n-ch v dd p-ch v dd p-ch output disable pull-up enable data in/out n-ch v dd p-ch v dd p-ch in comparator v ref (threshold voltage) + input enable p-ch n-ch n-ch out 13 m pd78p368a 2. memory configuration the m pd78p368a can access memory of up to 64k bytes. fig. 2-1 shows the memory map. fig. 2-1 memory map note access in the external memory expansion mode. caution when word access (including the stack operation) to the main ram space (fe00h to feffh) is executed, the addresses specified in the operand must be even numbers. special function register (sfr) ffffh ff00h feffh memory space (64k 8) program memory data memory f700h c000h 0000h main ram (256 8) general register (128 8) macro service control (32 8) data area (2048 8) feffh fe80h fe25h fe06h f700h callf instruction entry area (2048 8) program area callt instruction table area (64 8) vector table area (64 8) bfffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h data memory program area 1000h 0fffh internal prom (49152 8) bfffh external memory note (14080 8) (256 8) f6ffh peripheral ram (1792 8) fe00h fdffh mode 0, 1 = ll 14 m pd78p368a 3. differences between the m m m m m pd78p368a and m m m m m pd78366a the m pd78p368a is produced by replacing the internal mask rom of the m pd78366a with a 48k-byte prom. both have the same functions except some differences in rom specifications, such as write and verify modes. table 3-1 shows the differences. in this manual, the functions specific to the m pd78p368a are explained. for details of the other functions, refer to the m pd78366a document. table 3-1 differences between the m m m m m pd78p368a and m pd78366a cautions 1. the prom and mask rom products differ in noise immunity and noise radiation. use not es products but cs products (mask rom products) to evaluate them thoroughly when considering the change from the prom products to the mask rom products during processes from preproduction to volume production. 2. connect the mode0 and mode1 pins directly to the v dd or v ss pin. item 48k bytes one-time prom (data can be written once) eprom (data can be written multiple times) 32k bytes mask rom provided not provided rom internal program memory (electrical write) prom programming pin setting of mode0 and mode1 package electrical characteristics others ? normal operation mode mode0, 1 = ll ? prom programming mode mode0, 1 = hl ? normal operation mode mode0, 1 = ll ? rom-less mode mode0, 1 = hh 80-pin plastic qfp 80-pin plastic qfp 80-pin ceramic wqfn they differ in supply current and other factors. since each product has a different circuit scale and mask layout, the noise immunity and noise radiation of each product differ. part number m pd78366a m pd78p368a 15 m pd78p368a 4. prom programming the m pd78p368a is provided with an electrically writable prom of 48k 8 bits. when programming this prom, use the mode0/v pp and mode1 pins to set the m pd78p368a to the prom programming mode. the m pd78p368a provides programming characteristics compatibility with the m pd27c1001a. table 4-1 pin functions in programming mode 4.1 operation mode to enter the program write/verify mode, set each pin as follows: mode0/v pp = h, mode1 = l. in addition, any of the operation modes listed in table 4-2 can be selected by setting the ce, oe, and pgm pins in this mode. set the m pd78p368a to the read mode in order to read the contents of prom. handle unused pins as described in pin configuration (2). table 4-2 operation modes for prom programming remark : l or h programming mode a0-a16 d0-d7 pgm ce oe normal operation mode p00-p07, p21, p20, p80-p85, p30 p40-p47 astb p91 p90 mode0/v pp mode1 function address input data input program pulse chip enable output enable program voltage mode control mode page data latch page program byte program program verify program inhibit read output disable standby mode1 ce h h l l l l h oe l h h l l h l h pgm h l l h l h h mode0/v pp d0-d7 data input high impedance data input data output high impedance data output high impedance high impedance v dd l +12.5 v +5 v +6.5 v +5 v 16 m pd78p368a 4.2 procedure for writing on prom (page program mode) the following is a procedure for writing on prom. (see fig. 4-1 .) in the page program mode, data is written in units of pages (four bytes). when write data completes midway of a page, latch ffh after the data so that the data fits into pages. (1) always set each pin as follows: mode0/v pp = h and mode1 = l. connect unused pins according to pin configuration (2). (2) apply +6.5 v to the v dd pin and +12.5 v to the v pp pin. (3) input an initial address to the a0 to a16 pins. (4) clear the page counter. (5) data latch mode. input write data to the d0 to d7 pins and input an active-low pulse to the oe pin. increment the address and the page counter. (6) repeat step (5) for a page (four bytes). (7) input a 0.1 ms program pulse (active low) to the pgm pin. (8) verify mode. checks if data has been written in prom. apply a low level to the ce pin, input an active-low pulse to the oe pin, and then read the write data from the d0 to d7 pins. repeat this for a page (four bytes). when verification completes, apply a high level to the ce pin. ? if data has been written, go to step (10). ? if not, repeat steps (7) and (8). if no data is written yet after the steps have been repeated 10 times, go to step (9). (9) assume the device to be defective and stop write operation. (10) increment the address. (11) repeat steps (4) to (10) until the address exceeds the last address. fig. 4-2 is a timing chart of these steps (2) to (9). 17 m pd78p368a fig. 4-1 flowchart of procedure for writing (page program mode) note if write data does not fill a page, latch ffh for the rest of the page. (1) (2) (3) (4) (5) (6) (7) (8) (10) (11) (9) start writing apply power supply voltage set an initial address clear the counter to 0 latch write data note input a program pulse increment the address increment the address and counter counter verify mode last address write is completed defective device < 4 bytes last address write failure (up to 9th) write failure (10th) = 4 bytes write succeeded > last address 18 m pd78p368a fig. 4-2 prom write/verify timing chart (page program mode) 4.3 procedure for writing on prom (byte program mode) the following is a procedure for writing on prom. (see fig. 4-3 .) (1) always set each pin as follows: mode0/v pp = h and mode1 = l. connect unused pins according to pin configuration (2). (2) apply +6.5 v to the v dd pin and +12.5 v to the mode0/v pp pin, and input a low-level signal to the ce pin. (3) input an initial address to the a0 to a16 pins. (4) input write data to the d0 to d7 pins. (5) input a 0.1 ms program pulse (active low) to the pgm pin. (6) verify mode. checks if data has been written in prom. input an active-low pulse to the oe pin and read the write data from the d0 to d7 pins. ? if data has been written, go to step (8). ? if not, repeat steps (4) to (6). if no data is written yet after the steps have been repeated 10 times, go to step (7). (7) assume the device to be defective and stop write operation. (8) increment the address. (9) repeat steps (4) to (8) until the address exceeds the last address. fig. 4-4 is a timing chart of these steps (2) to (7). page data latch page program program verify address input address input data input data output hi-z hi-z hi-z a2 - a16 a0, a1 d0 - d7 +12.5 v v dd mode0/ v pp +6.5 v v dd v dd ce (input) pgm (input) oe (input) 19 m pd78p368a fig. 4-3 flowchart of procedure for writing (byte program mode) (1) (2) (3) (4) (5) (6) (8) (9) (7) start writing write is completed defective device last address verify mode increment the address input a program pulse input write data set an initial address apply power supply voltage last address write failure (up to 9th) write failure (10th) write succeeded > last address 20 m pd78p368a fig. 4-4 prom write/verify timing chart (byte program mode) byte program program verify address input hi-z hi-z hi-z a0 - a16 d0 - d7 +12.5 v v dd mode0/ v pp +6.5 v v dd v dd ce (input) pgm (input) oe (input) data input data output 21 m pd78p368a 4.4 procedure for reading from prom the following is a procedure for reading out the contents of prom to the external data bus (d0 to d7). (1) always set each pin as follows: mode0/v pp = h and mode1 = l. connect unused pins according to pin configuration (2). (2) apply +5 v to the v dd and mode0/v pp pins. (3) input the address of data to be read into the a0 to a16 pins. (4) read mode (ce = l, oe = l) (5) output the data on the d0 to d7 pins. fig. 4-5 is a timing chart of these steps (2) to (5). fig. 4-5 prom read timing chart address input hi-z hi-z a0 - a16 d0 - d7 ce (input) oe (input) data output 22 m pd78p368a 5. erasure characteristics ( m pd78p368akl-s only) data written in the m pd78p368akl-s program memory can be erased (ffh); therefore users can write other data in the memory. to erase the written data, expose the erasure window to light with a wavelength shorter than approx. 400 nm. normally, ultraviolet light with a wavelength of 254 nm is employed. the amount of light required to completely erase the data is as follows: ? intensity of ultraviolet light erasing time: 15 w?s/cm 2 min. ? erasing time: 15 to 20 minutes (when using a 12,000 m w/cm 2 ultraviolet lamp. it may, however, take more time due to lamp deterioration, dirt on the erasure window, or the like.) the ultraviolet lamp should be placed within 2.5 cm from the erasure window during erasure. in addition, if a filter is attached to the ultraviolet lamp, remove the filter before erasure. 6. protective film covering the erasure window ( m m m m m pd78p368akl-s only) after the erasure window of the m pd78p368akl-s has been exposed to sunlight or a fluorescent lamp for a long time, data in eprom may be erased and the internal circuits may malfunction. to prevent these failures, the erasure window should be covered with a protective film when it is not used for erasure. eprom package products with a window are supplied with a nec-guaranteed protective film when they are delivered. 7. screening one-time prom products nec cannot execute a complete test of one-time prom products ( m pd78p368agf-3b9) due to their structure before shipment. it is recommended that you screen (verify) prom products after writing necessary data into them and storing them at 125 c for 24 hours. nec offers a charged service called qtop microcomputer service. this service includes writing to one-time prom, marking, screening, and verification. ask your sales representative for details. 23 m pd78p368a 8. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit power supply voltage v dd C0.5 to +7.0 v av dd C0.5 to v dd + 0.5 v v pp C0.5 to +13.5 v av ss C0.5 to +0.5 v input voltage v i pins other than C0.5 to v dd + 0.5 v p70/ani0-p77/ani7 output voltage v o C0.5 to v dd + 0.5 v low-level output current i ol note 20 ma output pins other than 4.0 ma those in the note total of all output pins 200 ma high-level output current i oh all output pins C3.0 ma total of all output pins C25 ma analog input voltage v ian p70/ani0-p77/ani7 pins av ss C 0.5 to av dd + 0.5 v a/d converter reference input voltage av ref av ss C 0.5 to av dd + 0.5 v operating ambient temperature t a C40 to +85 c storage temperature t stg C60 to +150 c note p00/rtp0-p03/rtp3, p04/pwm0, p05/tcud/pwm1, p06/tiud/to40, p07/tclrud, p10-p17, and p80/to00-p85/to05 pins. caution absolute maximum ratings are rated values beyond which some physical damages may be caused to the product; if any of the parameters in the table above exceeds its rated value even for a moment, the quality of the product may deteriorate. be sure to use the product within the rated values. recommended operating conditions oscillation frequency t a v dd 3 mhz - f xx - 8 mhz C40 to +85 c +5.0 v 10 % capacitance (t a = 25 c, v ss = v dd = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i f = 1 mhz 20 pf output capacitance c o 0 v except measured pins 20 pf i/o capacitance c io 20 pf h 24 m pd78p368a oscillator characteristics (t a = C40 to +85 c, v dd = +5 v 10 %, v ss = 0 v) resonator recommended circuit parameter min. max. unit ceramic resonator or oscillation frequency (f xx ) 3 8 mhz crystal external clock x1 input frequency (f x ) 3 8 mhz x1 rise/fall time (t xr , t xf )030ns x1 input high-/low-level 40 170 ns width (t wxh , t wxl ) caution when using system clock oscillation circuits, to reduce the effect of the wiring capacitance, etc, wire the area indicated by dotted-line as follows: ? make the wiring as short as possible. ? do not allow the wiring to intersect other signal lines. keep it away from other lines in which varying high currents flow. ? make sure that the ground point of the oscillation circuit capacitor is always at the same electric potential as v ss . do not allow the wiring to be grounded to a ground pattern in which very high currents are flowing. ? do not extract signals from the oscillation circuit. v ss x2 x1 c1 c2 open hcmos inverter x1 x2 25 m pd78p368a dc characteristics (t a = C40 to +85 c, v dd = +5 v 10 %, v ss = 0 v) parameter symbol conditions min. typ. max. unit low-level input voltage v il1 note 1 0 0.8 v v il2 note 2 0 0.2v dd v high-level input voltage v ih1 note 1 2.2 v v ih2 note 2 0.8v dd v low-level output voltage v ol1 note 3 i ol = 2.0 ma 0.45 v v ol2 note 4 i ol = 15 ma 1.5 v v ol3 note 5 i ol = 10 ma 1.5 v high-level output voltage v oh i oh = C400 m a v dd C 1.0 v input leakage current i li 0 v - v i - v dd , av dd = v dd 10 m a output leakage current i lo 0 v - v o - v dd , av dd = v dd 10 m a v dd supply current i dd1 operating mode 70 120 ma i dd2 halt mode 45 70 ma data retention voltage v dddr stop mode 2.5 v data retention current i dddr stop mode v dddr = 2.5 v 2 10 m a v dddr = 5.0 v 10 % 10 50 m a pull-up resistance r l v i = 0 v 15 60 150 k y notes 1. pins other than those specified in note 2 . 2. reset, x1, x2, p20/nmi, p21/intp0, p22/intp1, p23/intp2, p24/intp3/ti, p25/intp4, p32/so/ sb0, p33/si/sb1 and p34/sck pins. 3. pins other than those specified in notes 4 and 5 . 4. p80/to00-p85/to05 pins (when i ol = 15 ma is in operation, up to three pins can be on simultane- ously.) 5. p00/rtp0-p03/rtp3, p04/pwm0, p05/tcud/pwm1, p06/tiud/to40 and p07/tclrud pins (when i ol = 10 ma is in operation, up to four pins can be on simultaneously.) as well as p10-p17 pins (when i ol = 10 ma is in operation, up to four pins can be on simultaneously.). caution when the p80-p85, p00-p07, and p10-p17 pins are not used under the conditions specified in notes 4 and 5, they have the same characteristics as in note 3. 26 m pd78p368a ac characteristics (t a = C40 to +85 c, v dd = +5 v 10 %, v ss = 0 v, c l = 100 pf, f xx = 8 mhz) read/write operation (when general-purpose memory is connected) parameter symbol conditions min. max. unit system clock cycle time t cyk 62.5 166.7 ns address setup time (vs. astb ? )t sast 7ns address hold time (vs. astb ? )t hsta 11 ns rd ? ? address float time t fra 24 ns address ? data input time t daid 100 ns rd ? ? data input time t drid 49 ns astb ? ? rd ? delay time t dstr 15 ns data hold time (vs. rd ? )t hrid 0ns rd ? ? address active time t dra 17 ns rd low-level width t wrl 63 ns astb high-level width t wsth 14 ns wr ? ? data output time t dwod 21 ns astb ? ? wr ? delay time t dstw 15 ns wr ? ? astb ? delay time t dwst 78 ns data setup time (vs. wr ? )t sodw 57 ns data hold time (vs. wr ? )t hwod 8ns wr low-level width t wwl 63 ns t cyk -dependent bus timing definition parameter arithmetic expression min./max. unit t sast (0.5 + a) t C 24 min. ns t hsta 0.5t C 20 min. ns t wsth (0.5 + a) t C 17 min. ns t dstr 0.5t C 16 min. ns t wrl (1.5 + n) t C 30 min. ns t daid (2.5 + a + n) t C 56 max. ns t drid (1.5 + n) t C 44 max. ns t dra 0.5t C 14 min. ns t dstw 0.5t C 16 min. ns t dwst 1.5t C 15 min. ns t wwl (1.5 + n) t C 30 min. ns t dwod 0.5t C 10 max. ns t sodw (1 + n) t C 5 min. ns remarks 1. t = t cyk = 1/f clk (f clk refers to the internal system clock frequency.) 2. a becomes 1 when the address wait is inserted. otherwise, it becomes 0. 3. n refers to the number of wait cycles that is inserted by specifying the pwc register. 4. only the bus timings indicated in this table depend on t cyk . 27 m pd78p368a serial operation (t a = C40 to +85 c, v dd = +5 v 10 %, v ss = 0 v) parameter symbol conditions min. max. unit serial clock cycle time t cysk sck output internal 8 dividing 500 ns sck input external clock 500 ns serial clock low-level width t wskl sck output internal 8 dividing 210 ns sck input external clock 210 ns serial clock high-level width t wskh sck output internal 8 dividing 210 ns sck input external clock 210 ns si setup time (vs. sck ? ) t srxsk 80 ns si hold time (vs. sck ? )t hskrx 80 ns sck ? ? so delay time t dsktx r = 1 ky, c = 100 pf 210 ns up/down counter operation (t a = C40 to +85 c, v dd = +5 v 10 %, v ss = 0 v) parameter symbol conditions min. max. unit tiud high-/low-level width t wtiuh , t wtiul other than mode 4 2t ns mode 4 4t ns tcud high-/low-level width t wtcuh , t wtcul other than mode 4 2t ns mode 4 4t ns tclrud high-/low-level width t wcluh , t wclul 2t ns tcud setup time (vs. tiud ? ) t stcu mode 3 t ns tcud hold time (vs. tiud ? ) t htcu mode 3 t ns tiud setup time (vs. tcud) t s4tiu mode 4 2t ns tiud hold time (vs. tcud) t h4tiu mode 4 2t ns tiud & tcud cycle time t cyc other than mode 4 4 mhz t cyc4 mode 4 2 mhz remark t = t cyk = 1/f clk (f clk refers to the internal system clock frequency.) 28 m pd78p368a other operations (t a = C40 to +85 c, v dd = +5 v 10 %, v ss = 0 v) parameter symbol conditions min. max. unit nmi high-/low-level width t wnih , t wnil 2 m s reset high-/low-level width t wrsh , t wrsl 1.5 m s intp0 high-/low-level width t wi0h , t wi0l ts = t 250 ns ts = 4t 1.0 m s ts = 8t 2.0 m s ts = 16t 4.0 m s intp1 high-/low-level width t wi1h , t wi1l ts = t 250 ns ts = 4t 1.0 m s ts = 8t 2.0 m s ts = 16t 4.0 m s intp2 high-/low-level width t wi2h , t wi2l ts = t 250 ns ts = 4t 1.0 m s intp3(ti) high-/low-level width t wi3h , t wi3l ts = t 250 ns ts = 4t 1.0 m s ts = 8t 2.0 m s ts = 16t 4.0 m s ts = 64t 16.0 m s ts = 128t 32.0 m s ts = 256t 64.0 m s intp4 high-/low-level width t wi4h , t wi4l ts = t 250 ns ts = 4t 1.0 m s ts = 8t 2.0 m s ts = 16t 4.0 m s remarks 1. t = t cyk = 1/f clk (f clk refers to the internal system clock frequency.) 2. ts refers to the input sampling frequency. intp0-intp4 can be selected to programmable. 29 m pd78p368a a/d converter characteristics (t a = C40 to +85 c, v dd = +5 v 10 %, v ss = av ss = 0 v, v dd C 0.5 v - av dd - v dd ) parameter symbol conditions min. typ. max. unit resolution 10 bit total error note 1 4.5 v - av ref - av dd 0.4 %fsr 3.4 v - av ref - av dd 0.7 %fsr quantization error 1/2 lsb conversion time t conv 62.5 ns - t cyk < 80 ns 208 t cyk 80 ns - t cyk - 166.6 ns 169 t cyk sampling time t samp 62.5 ns - t cyk < 80 ns 8 t cyk 80 ns - t cyk - 166.6 ns 6 t cyk zero-scale error note 1 4.5 v - av ref - av dd 1.5 2.5 lsb 3.4 v - av ref - av dd 1.5 4.5 lsb full-scale error note 1 4.5 v - av ref - av dd 1.5 2.5 lsb 3.4 v - av ref - av dd 1.5 4.5 lsb nonlinearity error note 1 4.5 v - av ref - av dd 1.5 2.5 lsb 3.4 v - av ref - av dd 1.5 4.5 lsb analog input voltage note 2 v ian C0.3 av ref + 0.3 v analog input impedance r an when not sampling 10 m w when sampling note 3 reference voltage av ref 3.4 av dd v av ref1 current ai ref 1.0 3.0 ma av dd supply current ai dd operating mode 2.0 6.0 ma a/d converter data ai dddr stop mode av dddr = 2.5 v 2 10 m a retention current av dddr = 5 v 10 % 10 50 m a notes 1. the quantization error is excluded. 2. when C0.3 v - v ian - 0 v, the conversion result becomes 000h. when 0 v < v ian < av ref , the conversion is performed with the 10-bit resolution. when av ref - v ian - av ref + 0.3 v, the conversion result becomes 3ffh. 3. the analog input impedance at the time of sampling is the same as the equivalent circuit shown below. (the values in the diagram are typ. values; they are not guaranteed values.) analog input pin 25 pf (input capacitance included) 1.4 pf 1 k w 30 m pd78p368a cautions 1. when using the p70/ani0-p77/ani7 pins for both digital and analog inputs, the previously described characteristics are not guaranteed. therefore, ensure that all of the eight p70/ ani0-p77/ani7 pins are used either for analog input or digital input. 2. when using the p70/ani0-p77/ani7 pins as digital input, make sure to set that av dd = v dd , and av ss = v ss . ac timing test point 0.8v dd or 2.2 v 0.2v dd or 0.8 v 0.8v dd or 2.2 v 0.2v dd or 0.8 v v dd 0 v test point 31 m pd78p368a read operation write operation a8 - a15 (output) ad0 - ad7 (input/output) astb (output) rd (output) t wsth t sast t daid hi-z hi-z hi-z hi-z high-order address high-order address t cyk t hsta t fra t dstr t drid t dra t wrl t hrid low-order address (output) low-order address (output) data (input) (clk) a8 - a15 (output) ad0 - ad7 (output) astb (output) wr (output) t wsth t sast high-order address high-order address t hsta t dstw t dwod t wwl low-order address (output) low-order address (output) data (output) (clk) t hwod t dwst undefined t sodw 32 m pd78p368a serial operation up/down counter (timer 4) input timing t cysk t wskl t wskh t dsktx t srxsk t hskrx sck so si t wtiuh t stcu t htcu t wtiul t wtcul t wtcuh tiud tcud t wcluh t wclul tclrud tiud tcud t s4tiu t h4tiu t s4tiu t h4tiu 33 m pd78p368a interrupt input timing remark n = 0 C 4 reset input timing t wnih t wnil 0.8v dd 0.2v dd nmi t winh t winl intpn 0.8v dd 0.2v dd t wrsh t wrsl 0.8v dd 0.2v dd reset 34 m pd78p368a dc programming characteristics (t a = 25 5 c, v ss = 0 v) min. 2.4 C0.3 2.4 6.25 4.5 12.2 v dd C 0.6 typ. 6.5 5.0 12.5 v dd unit v v m a v v m a v v v v ma ma ma m a max. v ddp + 0.3 0.8 10 0.45 10 6.75 5.5 12.8 v dd + 0.6 50 50 50 100 parameter high-level input voltage low-level input voltage input leakage current high-level output voltage low-level output voltage output leakage current v ddp supply voltage v pp supply voltage v ddp supply current v pp supply current symbol v ih v il i lip v oh v ol i lo v ddp v pp i dd i pp symbol note 1 v ih v il i li v oh v ol C v cc v pp i dd i pp conditions 0 - v i - v ddp note 2 i oh = C400 m a i ol = 2.1 ma 0 - v o - v ddp , oe = v ih program memory write mode program memory read mode program memory write mode program memory read mode program memory write mode program memory read mode program memory write mode program memory read mode notes 1. symbols for the corresponding m pd27c1001a 2. the v ddp represents the v dd pin as viewed in the programming mode. 35 m pd78p368a ac programming characteristics (t a = 25 5 c, v ss = 0 v) prom write mode (page program mode) parameter address set up time ce set time input data setup time address hold time input data hold time output data hold time v pp setup time v ddp setup time initial program pulse width oe set time valid data delay time from oe oe pulse width in the data latch pgm setup time ce hold time oe hold time symbol note 1 t as t ces t ds t ah t ahl t ahv t dh t df t vps t vds note 2 t pw t oes t oe t lw t pgms t ceh t oeh notes 1. these symbols (except t vds ) correspond to those of the m pd27c1001a. 2. for m pd27c1001a, read t vds as t vcs . min. 2 2 2 2 2 0 2 0 1 1 0.095 2 1 2 2 2 typ. max. 250 0.105 1.0 unit m s m s m s m s m s m s m s ns ms ms ms m s m s m s m s m s m s conditions 36 m pd78p368a prom write mode (byte program mode) parameter address set up time ce set time input data setup time address hold time input data hold time output data hold time v pp setup time v ddp setup time initial program pulse width oe set time valid data delay time from oe symbol note 1 t as t ces t ds t ah t dh t df t vps t vds note 2 t pw t oes t oe notes 1. these symbols (except t vds ) correspond to those of the m pd27c1001a. 2. for m pd27c1001a, read t vds as t vcs . prom read mode note these symbols correspond to those of the m pd27c1001a. symbol note t acc t ce t oe t df t oh min. 0 0 typ. max. 1.0 1.0 1.0 250 unit m s m s m s ns ns conditions ce = oe = v il oe = v il ce = v il ce = v il ce = oe = v il min. 2 2 2 2 2 0 1 1 0.095 2 typ. max. 250 0.105 1.0 unit m s m s m s m s m s ns ms ms ms m s m s conditions parameter data output time from address ce ? ? data output time oe ? ? data output time data hold time to oe ? data hold time to address 37 m pd78p368a prom write mode timing (page program mode) page data latch page program program verify data output hi-z hi-z hi-z a2 - a16 a0, a1 d0 - d7 v pp v ddp v pp v ddp + 1.5 v ddp v ddp ce pgm oe v ih v il v ih v il v ih v il t as t ahl t ds t dh t vps data input t pgms t oe t vds t ahv t df t ah t oeh t ces t ceh t pw t oes t lw 38 m pd78p368a prom write mode timing (byte program mode) cautions 1. v ddp must be applied before v pp , and must be cut after v pp . 2. v pp including overshoot must not exceed +13.5 v. 3. plugging in or out the board with the v pp pin supplied with +12.5 v may adversely affect its reliability. prom read mode timing notes 1. for reading within t acc , the delay of the oe input from falling edge of ce must be within t acc C t oe . 2. t df is the time measured from when either oe or ce reaches v ih , whichever is faster. program program verify a0 - a16 v pp v ddp v pp v ddp + 1.5 v ddp v ddp ce pgm v ih v il v ih v il t pw hi-z hi-z hi-z d0 - d7 v ih v il t as t ds t vps t vds t ces t df t ah t dh t oes t oe data input data output oe a0 - a16 ce oe hi-z hi-z d0 - d7 data output t ce valid address t acc note 1 t oh t oe note 1 t df note 2 39 m pd78p368a 9. package drawings 80 pin plastic qfp (14 20) note each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. detail of lead end m f g h i j k m l n p q r item millimeters inches s p80gf-80-3b9-3 3.0 max. 0.119 max. k 1.8?.2 0.071 +0.008 ?.009 l 0.8?.2 0.031 +0.009 ?.008 p 2.7 0.106 n 0.10 0.004 m 0.15 0.006 +0.004 ?.003 q 0.1?.1 0.004?.004 a 23.6?.4 0.929?.016 b 20.0?.2 0.795 +0.009 ?.008 c 14.0?.2 0.551 +0.009 ?.008 g f 0.8 1.0 0.031 0.039 d 17.6?.4 0.693?.016 j 0.8 (t.p.) 0.031 (t.p.) i 0.15 0.006 h 0.35?.10 0.014 +0.004 ?.005 +0.10 ?.05 64 65 40 80 1 25 24 41 a b cd s r5 ? 5 ? 40 m pd78p368a 80 pin ceramic wqfn note each lead centerline is located within 0.08 mm (0.003 inch) of its true position (t.p.) at maximum material condition. x80kw-80a1 item millimeters inches a b c d f g h i j k q r s t u1 w 20.0 0.25 19.0 13.4 14.2 0.2 1.84 c0.3 7.62 2.6 0.08 0.8 (t.p.) 3.56max. 0.51 0.1 0.072 0.141max. 0.787 +0.011 ?.010 0.748 0.528 0.559 0.008 0.003 0.031 (t.p.) 0.02 0.004 c0.012 0.102 0.3 0.10 z 0.004 ff a c d f h i m b u1 t g k w jr 80 q z 1 s 1.0?.15 0.039 + 0.007 0.006 0.8 0.031 1.1 0.043 0.75?.15 0.03 +0.006 ? 0.007 41 m pd78p368a 10. recommended soldering conditions these products should be soldered and mounted under the conditions recommended below. for details of recommended soldering conditions, refer to the information document semiconductor device mounting technology manual (c10535j). for soldering methods and conditions other than those recommended, please contact your nec sales representative. table 10-1. surface mount type soldering conditions m pd78p368agf-3b9: 80-pin plastic qfp (14 20 mm) note maximum number of days during which the product can be stored at a temperature of 25 c and a relative humidity of 65 % or less after dry-pack package is opened. caution use of more than one soldering method should be avoided (except in the case of partial heating). recommended condition symbol ir35-207-2 vp15-207-2 ws60-207-1 C soldering method infrared reflow vps wave soldering partial heating h soldering conditions package peak temperature: 235 c, duration: 30 sec. max. (210 c or above) number of times: 2 max. exposure limit: 7 days note (20 hours of pre-baking is required at 125 c afterward) 42 m pd78p368a appendix a tools a.1 development tools the following tools are provided for developing a system that uses the m pd78p368a: language processor this relocatable program can be used for all 78k/iii series emulators. with its macro functions, it allows the user to improve program development efficiency. a structured-programming assembler is also provided, which enables explicit description of program control structures. this assembler could improve produc- tivity in program production and maintenance. 78k/iii series relocatable assembler (ra78k3) distribution media 3.5-inch 2hd 5.25-inch 2hd 3.5-inch 2hc 5.25-inch 2hc dat cartridge tape (qic-24) part number m s5a13ra78k3 m s5a10ra78k3 m s7b13ra78k3 m s7b10ra78k3 m s3p16ra78k3 m s3k15ra78k3 m s3r15ra78k3 os ms-dos tm pc dos tm hp-ux tm sunos tm news-os tm host machine pc-9800 series ibm pc/at tm or compatibles hp9000 series 700 tm sparcstation tm news tm os ms-dos pc dos hp-ux sunos news-os distribution media 3.5-inch 2hd 5.25-inch 2hd 3.5-inch 2hc 5.25-inch 2hc dat cartridge tape (qic-24) this c compiler can be used for all 78k/iii series emulators. the compiler converts programs written in c language into object codes executable on the microcomputer. when the compiler is used, the 78k/iii series relocatable assembler package (ra78k3) is needed. 78k/iii series c compiler (cc78k3) part number m s5a13cc78k3 m s5a10cc78k3 m s7b13cc78k3 m s7b10cc78k3 m s3p16cc78k3 m s3k15cc78k3 m s3r15cc78k3 host machine pc-9800 series ibm pc/at or compatibles hp9000 series 700 sparcstation news remark it is guaranteed that the relocatable assembler and c compiler run only under the oss on the corresponding host machines described above. 43 m pd78p368a prom programming tools remark it is guaranteed that the pg-1500 controller runs only under the oss on the corresponding host machines described above. debugging tools (when the ie controller is used) remark it is guaranteed that the ie controller runs only under the oss on the corresponding host machines described above. the pg-1500 prom programmer is used together with an accessory board and optional program adapter. it allows the user to program a single chip microcom- puter containing prom independently or from a host machine. the pg-1500 can be used to program typical 256k-bit to 4m-bit proms. programmer adapter for writing programs to the m pd78p368a. used with a prom programmer such as the pg-1500. pa-78p368gf : for m pd78p368agf pa-78p368kl : for m pd78p368akl this program enables the host machine to control the pg-1500 through the serial and parallel interfaces. hardware software os ms-dos pc dos host machine pc-9800 series ibm pc/at or compatibles distribution media 3.5-inch 2hd 5.25-inch 2hd 3.5-inch 2hc 5.25-inch 2hc part number m s5a13pg1500 m s5a10pg1500 m s7b13pg1500 m s7b10pg1500 pg-1500 pa-78p368gf pa-78p368kl pg-1500 controller hardware software in-circuit emulator for developing and debugging an application system. for debugging, connect the emulator to the host machine. i/o emulation board for emulating peripheral hardware such as the i/o ports of the target device. emulation probe for connecting the ie-78350-r to the target system. one ev-9200g-80 conversion socket is provided for connection to the target system. this control program allows the user to control the ie-78350-r from the host machine. its automatic command execution function ensures more efficient debugging. ie-78350-r ie-78365-r-em1 ep-78365gf-r ev-9200g-80 ie-78350-r control program (ie controller) part number m s5a13ie78365a m s5a10ie78365a m s7b13ie78365a m s7b10ie78365a distribution media 3.5-inch 2hd 5.25-inch 2hd 3.5-inch 2hc 5.25-inch 2hc os ms-dos pc dos host machine pc-9800 series ibm pc/at or compatibles h h h h 44 m pd78p368a configuration of development tools (when the ie controller is used) note the socket is supplied with the emulation probe. remarks 1. the pg-1500 can be directly connected to the host machine via the rs-232-c interface. 2. in this figure, the distribution media of software is represented by the 3.5-inch floppy disk. pa-78p368kl pa-78p368gf programmer adapter pd78p368akl pd78p368agf device containing prom + + + ep-78365gf-r ie-78350-r in-circuit emulator + ie-78365-r-em1 i/o emulation board (option) ev-9200g-80 emulation probe target system rs-232-c prom programmer pg-1500 socket for connecting the emulation probe and target system note rs-232-c host machine: pc-9800 series ibm pc/at ews mm relocatable assembler c compiler pg-1500 controller ie controller software 45 m pd78p368a debugging tools (when the integrated debugger is used) hardware software ie-784000-r ie-78350-r-em-a note ie-78365-r-em1 ep-78365gf-r ev-9200g-80 ie-70000-98-if-b ie-70000-98n-if ie-70000-pc-if-b ie-78000-r-sv3 integrated debugger (id78k3) device file (df78365) in-circuit emulator for developing and debugging an application system. for debugging, connect the emulator to the host machine. emulation board for emulating peripheral hardware such as the i/o ports of the target device. i/o emulation board for emulating peripheral hardware such as the i/o ports of the target device. emulation probe for connecting the ie-784000-r to the target system. one ev- 9200g-80 conversion socket is provided for connection to the target system. interface adapter when the pc-9800 series computer (other than a notebook) is used as the host machine. interface adapter and cable when a pc-9800 series notebook is used as the host machine. interface adapter when the ibm pc/at is used as the host machine. interface adapter and cable when the ews is used as the host machine. program for controlling the in-circuit emulator for the 78k/iii series. the inte- grated debugger (id78k3) is used together with the device file (df78365). debugging can be performed for the source program written in c, structured assembly language, or assembly language. the id78k3 can display various information simultaneously on the host machine screen divided into multiple areas. this ensures efficient debugging. pc-9800 series ibm pc/at or compatibles (japanese windows) ibm pc/at or compatibles (windows) file which contains the device-specific information. the device file (df78365) is used together with the assembler (ra78k3), c compiler (cc78k3), or integrated debugger (id78k3). pc-9800 series ibm pc/at or compatibles + + os ms-dos pc dos host machine host machine 3.5-inch 2hd 5.25-inch 2hd 3.5-inch 2hc 5.25-inch 2hc 3.5-inch 2hc 5.25-inch 2hc part number m saa13id78k3 m saa10id78k3 m sab13id78k3 m sab10id78k3 m sbb13id78k3 m sbb10id78k3 os ms-dos windows tm pc dos windows distribution media 3.5-inch 2hd 5.25-inch 2hd 3.5-inch 2hc 5.25-inch 2hc part number m s5a13df78365 m s5a10df78365 m s7b13df78365 m s7b10df78365 distribution media note under development remark it is guaranteed that the integrated debugger and device file run only under the oss on the corresponding host machines described above. 46 m pd78p368a configuration of development tools (when the integrated debugger is used) note the socket is supplied with the emulation probe. remarks 1. in this figure, the host machine is represented by the desktop personal computer. 2. in this figure, the distribution media of software is represented by the 3.5-inch floppy disk. pa-78p368kl pa-78p368gf programmer adapter pd78p368akl pd78p368agf device containing prom + + + ep-78365gf-r ev-9200g-80 emulation probe target system prom programmer pg-1500 socket for connecting the emulation probe and target system note ie-70000-98-if-b ie-70000-98n-if ie-70000-pc-if-b host machine: pc-9800 series ibm pc/at ews mm relocatable assembler c compiler rs-232-c pg-1500 controller integrated debugger software ie-784000-r in-circuit emulator + ie-78350-r-em-a emulation board (option) + ie-78365-r-em1 i/o emulation board (option) device file 47 m pd78p368a a.2 embedded software to improve the efficiency of program development and simplify the maintenance of systems incorporating this microcontroller, the following embedded software is provided. real-time os note under development caution before purchasing this software, complete the purchase application sheet and sign the software license agreement. remark to use the rx78k/iii real-time operating system, the optional ra78k3 assembler package is required. this operating system was designed to provide a multitasking environment for control applications that require real-time processing. system performance is improved by using the idling cpu for other processing. rx78k/iii provides system calls that conform to m itron specifications. the rx78k/iii package provides the rx78k/iii nucleus and a tool (configurator) that is used for creating multiple information tables. real-time os (rx78k/iii) note host machine os part number distribution media 3.5-inch 2hd 5.25-inch 2hd 3.5-inch 2hc 5.25-inch 2hc undecided undecided undecided undecided ms-dos pc dos pc-9800 series ibm pc/at or compatibles 48 m pd78p368a fuzzy inference development support system note under development this program supports the input/editing and simulation of fuzzy knowledge data (fuzzy rules and membership functions). tool for creating fuzzy knowledge data (fe9000, fe9200) host machine os part number distribution media this program converts fuzzy knowledge data, obtained using the tool for creating fuzzy knowledge data, into an assembler source program for ra78k3. translator (ft78k3) note host machine os part number this program performs fuzzy inference by linking the fuzzy knowledge data converted by translator. fuzzy inference module (fi78k/iii) note host machine os part number distribution media this software supports the evaluation and adjustment of fuzzy knowledge data at the hardware level, by using an in-circuit emulator. fuzzy inference debugger (fd78k/iii) host machine os part number distribution media distribution media m s5a13fd78k3 m s5a10fd78k3 m s7b13fd78k3 m s7b10fd78k3 3.5-inch 2hd 5.25-inch 2hd 3.5-inch 2hc 5.25-inch 2hc 3.5-inch 2hd 5.25-inch 2hd 3.5-inch 2hc 5.25-inch 2hc 3.5-inch 2hd 5.25-inch 2hd 3.5-inch 2hc 5.25-inch 2hc m s5a13fe9000 m s5a10fe9000 m s7b13fe9200 m s7b10fe9200 m s5a13ft78k3 m s5a10ft78k3 m s7b13ft78k3 m s7b10ft78k3 m s5a13fi78k3 m s5a10fi78k3 m s7b13fi78k3 m s7b10fi78k3 3.5-inch 2hd 5.25-inch 2hd 3.5-inch 2hc 5.25-inch 2hc pc-9800 series ibm pc/at or compatibles ms-dos pc dos windows + ms-dos pc dos pc-9800 series ibm pc/at or compatibles pc-9800 series ibm pc/at or compatibles ms-dos pc dos pc-9800 series ibm pc/at or compatibles ms-dos pc dos 49 m pd78p368a appendix b dimensions of the conversion socket and recommended pattern on boards fig. b-1 dimensions of the conversion socket (ev-9200g-80)(reference) a g e 1 f b c n o p m l t s j i r d u q ev-9200g-80 k h no.1 pin index ev-9200g-80-g0 item millimeters inches a b c d e f g h i j k l m o n p q r s t u 25.0 20.30 4.0 14.45 19.0 4-c 2.8 0.8 11.0 22.0 24.7 5.0 16.2 18.9 8.0 7.8 2.5 2.0 1.35 0.35 0.1 2.3 1.5 0.984 0.799 0.157 0.569 0.748 4-c 0.11 0.031 0.433 0.866 0.972 0.197 0.638 0.744 0.315 0.307 0.098 0.079 0.053 0.014 0.091 0.059 +0.004 ?.005 f f f f based on ev-9200g-80 (1) package drawing (in mm) 50 m pd78p368a fig. b-2 recommended pattern on boards for the conversion socket (ev-9200g-80)(reference) a f d e b g j k c l m h i 0.031 0.906=0.724 0.031 0.591=0.472 ev-9200g-80-p0 item millimeters inches a b c d e f g h i j k l m 25.7 21.0 15.2 19.9 11.00 0.08 5.50 0.03 5.00 0.08 2.50 0.03 0.5 0.02 2.36 0.03 1.57 0.03 1.012 0.827 0.598 0.783 0.433 0.217 0.197 0.098 0.02 0.093 0.062 0.8 0.02 23=18.4 0.05 0.8 0.02 15=12.0 0.05 f f +0.002 ?.001 +0.003 ?.002 +0.002 ?.001 +0.003 ?.002 +0.004 ?.003 +0.001 ?.002 +0.003 ?.004 +0.002 ?.001 +0.001 ?.002 f f +0.001 ?.002 +0.001 ?.002 based on ev-9200g-80 (2) pad drawing (in mm) dimensions of mount pad for ev-9200 and that for target device (qfp) may be different in some parts. for the recommended mount pad dimensions for qfp, refer to "semiconductor device mounting technology manual" (iei-1207). caution 51 m pd78p368a qtop is a trademark of nec corporation. ms-dos and windows are trademarks of microsoft corporation. pc/at and pc dos are trademarks of ibm corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sunos is a trademark of sun microsystems, inc. news and news-os are trademarks of sony corporation. tron stands for the realtime operating system nucleus. itron stands for industrial tron. cautions on cmos devices countermeasures against static electricity for all moss caution when handling mos devices, take care so that they are not electrostatically charged. strong static electricity may cause dielectric breakdown in gates. when transporting or storing mos devices, use conductive trays, magazine cases, shock absorbers, or metal cases that nec uses for packaging and shipping. be sure to ground mos devices during assembling. do not allow mos devices to stand on plastic plates or do not touch pins. also handle boards on which mos devices are mounted in the same way. cmos-specific handling of unused input pins caution hold cmos devices at a fixed input level. unlike bipolar or nmos devices, if a cmos device is operated with no input, an intermediate- level input may be caused by noise. this allows current to flow in the cmos device, resulting in a malfunction. use a pull-up or pull-down resistor to hold a fixed input level. since unused pins may function as output pins at unexpected times, each unused pin should be separately connected to the v dd or gnd pin through a resistor. if handling of unused pins is documented, follow the instructions in the document. statuses of all mos devices at initialization caution the initial status of a mos device is unpredictable when power is turned on. since characteristics of a mos device are determined by the amount of ions implanted in molecules, the initial status cannot be determined in the manufacture process. nec has no responsibility for the output statuses of pins, input and output settings, and the contents of registers at power on. however, nec assures operation after reset and items for mode setting if they are defined. when you turn on a device having a reset function, be sure to reset the device first. 52 m pd78p368a license not needed : m pd78p368akl-s the customer must judge the need for license : m pd78p368agf-3b9 the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices in "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 94. 11 |
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